GigaDevice Semiconductor GD32VF103 - Register Definition; RTC Control Register(RTC_CTL); RTC Interrupt Enable Register(RTC_INTEN)

GD32VF103 User Manual
217
14.4. Register definition
RTC base address: 0x4000 2800
14.4.1. RTC interrupt enable register(RTC_INTEN)
Address offset: 0x00
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
OVIE
ALRMIE
SCIE
rw
rw
rw
Bits
Fields
Descriptions
31:3
Reserved
Must be kept at reset value.
2
OVIE
Overflow interrupt enable
0: Disable overflow interrupt
1: Enable overflow interrupt
1
ALRMIE
Alarm interrupt enable
0: Disable alarm interrupt
1: Enable alarm interrupt
0
SCIE
Second interrupt enable
0: Disable second interrupt
1: Enable second interrupt
14.4.2. RTC control register(RTC_CTL)
Address offset: 0x04
Reset value: 0x0020
This register can be accessed by half-word (16-bit) or word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
LWOFF
CMF
RSYNF
OVIF
ALRMIF
SCIF
r
rw
rc_w0
rc_w0
rc_w0
rc_w0