GigaDevice Semiconductor GD32VF103 - APB2 Enable Register (RCU_APB2 EN)

GD32VF103 User Manual
83
3
Reserved
Must be kept at reset value
2
SRAMSPEN
SRAM interface clock enable when sleep mode
This bit is set and reset by software to enable/disable SRAM interface clock during
Sleep mode.
0: Disabled SRAM interface clock during Sleep mode.
1: Enabled SRAM interface clock during Sleep mode
1
DMA1EN
DMA1 clock enable
This bit is set and reset by software.
0: Disabled DMA1 clock
1: Enabled DMA1 clock
0
DMA0EN
DMA0 clock enable
This bit is set and reset by software.
0: Disabled DMA0 clock
1: Enabled DMA0 clock
5.3.7. APB2 enable register (RCU_APB2EN)
Address offset: 0x18
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
USART0
EN
Reserved
SPI0EN
TIMER0E
N
ADC1EN
ADC0EN
Reserved
PEEN
PDEN
PCEN
PBEN
PAEN
Reserved
AFEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:15
Reserved
Must be kept at reset value
14
USART0EN
USART0 clock enable
This bit is set and reset by software.
0: Disabled USART0 clock
1: Enabled USART0 clock
13
Reserved
Must be kept at reset value
12
SPI0EN
SPI0 clock enable
This bit is set and reset by software.
0: Disabled SPI0 clock
1: Enabled SPI0 clock