GigaDevice Semiconductor GD32VF103 - APB1 Reset Register (RCU_APB1 RST)

GD32VF103 User Manual
79
1: Reset the GPIO port C
3
PBRST
GPIO port B reset
This bit is set and reset by software.
0: No reset
1: Reset the GPIO port B
2
PARST
GPIO port A reset
This bit is set and reset by software.
0: No reset
1: Reset the GPIO port A
1
Reserved
Must be kept at reset value
0
AFRST
Alternate function I/O reset
This bit is set and reset by software.
0: No reset
1: Reset Alternate Function I/O
5.3.5. APB1 reset register (RCU_APB1RST)
Address offset: 0x10
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DACRST
PMURST
BKPIRST
CAN1RS
T
CAN0RS
T
Reserved
I2C1RST
I2C0RST
UART4R
ST
UART3R
ST
USART2
RST
USART1
RST
Reserved
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI2RST
SPI1RST
Reserved
WWDGT
RST
Reserved
TIMER6R
ST
TIMER5R
ST
TIMER4R
ST
TIMER3R
ST
TIMER2R
ST
TIMER1R
ST
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:30
Reserved
Must be kept at reset value
29
DACRST
DAC reset
This bit is set and reset by software.
0: No reset
1: Reset DAC unit
28
PMURST
Power control reset
This bit is set and reset by software.
0: No reset