GigaDevice Semiconductor GD32VF103 - Control Register 0 (ADC_CTL0)

GD32VF103 User Manual
175
Cleared by software writing 0 to it or by reading the ADC_RDATA register.
0
WDE
Analog watchdog event flag
0: No analog watchdog event
1: Analog watchdog event
Set by hardware when the converted voltage crosses the values programmed in the
ADC_WDLT and ADC_WDHT registers. Cleared by software writing 0 to it.
11.8.2. Control register 0 (ADC_CTL0)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
RWDEN
IWDEN
Reserved
SYNCM[3:0]
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DISNUM[2:0]
DISIC
DISRC
ICA
WDSC
SM
EOICIE
WDEIE
EOCIE
WDCHSEL[4:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:24
Reserved
Must be kept at reset value
23
RWDEN
Regular channel analog watchdog enable
0: Regular channel analog watchdog disable
1: Regular channel analog watchdog enable
22
IWDEN
Inserted channel analog watchdog enable
0: Inserted channel analog watchdog disable
1: Inserted channel analog watchdog enable
21:20
Reserved
Must be kept at reset value
19:16
SYNCM[3:0]
Sync mode selection
These bits use to select the operating mode.
0000: Free mode.
0001: Combined regular parallel + inserted parallel mode
0010: Combined regular parallel + trigger rotation mode
0011: Combined inserted parallel + follow-up fast mode
0100: Combined inserted parallel + follow-up slow mode
0101: Inserted parallel mode only
0110: Regular parallel mode only
0111: Follow-up fast mode only
1000: Follow-up slow mode only