GigaDevice Semiconductor GD32VF103 - I2 S Function Overview; I2 S Audio Standards; Figure 18-12. I2 S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0); Figure 18-13. I2 S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)

GD32VF103 User Manual
392
18.9. I2S function overview
18.9.1. I2S audio standards
The I2S audio standard is selected by the I2SSTD bits in the SPI_I2SCTL register. Four audio
standards are supported, including I2S Phillips standard, MSB justified standard, LSB justified
standard, and PCM standard. All standards except PCM handle audio data time-multiplexedly
on two channels (the left channel and the right channel). For these standards, the I2S_WS
signal indicates the channel side. For PCM standard, the I2S_WS signal indicates frame
synchronization information.
The data length and the channel length are configured by the DTLEN bits and CHLEN bit in
the SPI_I2SCTL register. Since the channel length must be greater than or equal to the data
length, four packet types are available. They are 16-bit data packed in 16-bit frame, 16-bit
data packed in 32-bit frame, 24-bit data packed in 32-bit frame, and 32-bit data packed in 32-
bit frame. The data buffer for transmission and reception is 16-bit wide. In the case that the
data length is 24 bits or 32 bits, two write or read operations to or from the SPI_DATA register
are needed to complete the transmission of a frame. In the case that the data length is 16
bits, only one write or read operation to or from the SPI_DATA register is needed to complete
the transmission of a frame. When using 16-bit data packed in 32-bit frame, 16-bit 0 is
inserted by hardware automatically to extend the data to 32-bit format.
For all standards and packet types, the most significant bit (MSB) is always sent first. For all
standards based on two channels time-multiplexed, the channel left is always sent first
followed by the channel right.
I2S Phillips standard
For I2S Phillips standard, I2S_WS and I2S_SD are updated on the falling edge of I2S_CK.
The timing diagrams for each configuration are shown below.
Figure 18-12. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0)
I2S_CK
I2S_SD
16-bit data
frame 1 (channel left) frame 2 (channel right)
MSB MSBLSB
I2S_WS
Figure 18-13. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1)
I2S_CK
I2S_SD
16-bit data
frame 1 (channel left) frame 2 (channel right)
MSB MSBLSB
I2S_WS
When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation