GigaDevice Semiconductor GD32VF103 - Register Definition

GD32VF103 User Manual
205
13.1.4. Register definition
FWDGT base address: 0x4000 3000
Control register (FWDGT_CTL)
Address offset: 0x00
Reset value: 0x0000 0000
This register can be accessed by half-word (16-bit) or word (32-bit) access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CMD[15:0]
w
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
CMD[15:0]
Write only. Several different fuctions are realized by writing these bits with different
values:
0x5555: Disable the FWDGT_PSC and FWDGT_RLD write protection.
0xCCCC: Start the free watchdog counter. When the counter reduces to 0, the free
watchdog generates a reset.
0xAAAA: Reload the counter.
Prescaler register (FWDGT_PSC)
Address offset: 0x04
Reset value: 0x0000 0000
This register can be accessed by half-word (16-bit) or word (32-bit) access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
PSC[2:0]
rw
Bits
Fields
Descriptions
31:3
Reserved
Must be kept at reset value
2:0
PSC[2:0]
Free watchdog timer prescaler selection. Write 0x5555 in the FWDGT_CTL register
before writing these bits. During a write operation to this register, the PUD bit in the