GigaDevice Semiconductor GD32VF103 - Register Definition; Backup Data Register X (Bkp_Datax) (X= 0; RTC Signal Output Control Register (BKP_OCTL)

GD32VF103 User Manual
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4.4. Register definition
BKP base address: 0x4000 6C00
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41)
Address offset: 0x04 to 0x28, 0x40 to 0xBC
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA [15:0]
rw
Bits
Fields
Descriptions
15:0
DATA[15:0]
Backup data
These bits are used for general purpose data storage. The contents of the
BKP_DATAx register will remain even if the wake-up action from Standby mode or
system reset or power reset occurs.
4.4.2. RTC signal output control register (BKP_OCTL)
Address offset: 0x2C
Reset value: 0x0000(bit [6:0], bit 8, bit 9 reset by a Backup domain reset, bit 7 reset by a POR/PDR)
This register can be accessed by half-word(16-bit) or word(32-bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ROSEL
ASOEN
COEN
RCCV[6:0]
rw
rw
rw
rw
Bits
Fields
Descriptions
15:10
Reserved
Must be kept at reset value.
9
ROSEL
RTC output selection
0: RTC alarm pulse is selected as the RTC output
1: RTC second pulse is selected as the RTC output
8
ASOEN
RTC alarm or second signal output enable
0: Disable RTC alarm or second output
1: Enable RTC alarm or second output
When enable, the TAMPER pin will output the RTC output.
7
COEN
RTC clock calibration output enable
0: Disable RTC clock calibration output