GigaDevice Semiconductor GD32VF103 - Figure 9-3. DMA Interrupt Logic; Interrupt; Table 9-2. Interrupt Events

GD32VF103 User Manual
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5. Configure the memory and peripheral transfer width, memory and peripheral address
generation algorithm in the DMA_CHxCTL register.
6. Configure the enable bit for full transfer finish interrupt, half transfer finish interrupt,
transfer error interrupt in the DMA_CHxCTL register.
7. Configure the DMA_CHxPADDR register for setting the peripheral base address.
8. Configure the DMA_CHxMADDR register for setting the memory base address.
9. Configure the DMA_CHxCNT register to set the total transfer data number.
10. Configure the CHEN bit with ‘1’ in the DMA_CHxCTL register to enable the channel.
9.4.8. Interrupt
Each DMA channel has a dedicated interrupt. There are three types of interrupt event,
including full transfer finish, half transfer finish, and transfer error.
Each interrupt event has a dedicated flag bit in the DMA_INTF register, a dedicated clear bit
in the DMA_INTC register, and a dedicated enable bit in the DMA_CHxCTL register. The
relationship is described in the following Table 9-2. Interrupt events.
Table 9-2. Interrupt events
Interrupt event
Flag bit
Clear bit
Enable bit
DMA_INTF
DMA_INTC
DMA_CHxCTL
Full transfer finish
FTFIF
FTFIFC
FTFIE
Half transfer finish
HTFIF
HTFIFC
HTFIE
Transfer error
ERRIF
ERRIFC
ERRIE
The DMA interrupt logic is shown in theFigure 9-3. DMA interrupt logic, an interrupt can be
produced when any type of interrupt event occurs and enabled on the channel.
Figure 9-3. DMA interrupt logic
and
and
and
or
FTFIFx
FTFIEx
HTFIFx
HTFIEx
ERRIFx
ERRIEx
CHxINTF
Note: “x” indicates channel number (for DMA0, x=0…6, for DMA1, x=0…4).