GigaDevice Semiconductor GD32VF103 - Host Control and Status Registers

GD32VF103 User Manual
498
31
30
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16
IEPTXFD
[15:0]
r/rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IEPTX
R
SAR
15:0]
r/rw
Bits
Fields
Descriptions
31:16
IEPTXFD[15:0]
IN endpoint Tx FIFO depth
In terms of 32-bit words.
1≤HPTXFD≤1024
15:0
IEPTXRSAR[15:0]
IN endpoint FIFO Tx RAM start address
The start address for IN endpoint transmit FIFOx is in term of 32-bit words.
21.7.2. Host control and status registers
Host control register (USBFS_HCTL)
Address offset: 0x0400
Reset value: 0x0000 0000
This register configures the core after power on in host mode. Do not modify it after host
initialization.
This register has to be accessed by word (32-bit)
31
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22
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18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CLKSEL
[1:0]
rw