GigaDevice Semiconductor GD32VF103 - Erase;Program Protection Register (FMC_WP); Option Byte Status Register (FMC_OBSTAT)

GD32VF103 User Manual
45
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR[31:16]
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR[15:0]
w
Bits
Fields
Descriptions
31:0
ADDR[31:0]
Flash erase/program command address bits
These bits are configured by software.
ADDR bits are the address of flash erase/program command
2.4.7. Option byte status register (FMC_OBSTAT)
Address offset: 0x1C
Reset value: 0x0XXX XXXX.
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DATA[15:6]
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[5:0]
USER[7:0]
SPC
OBERR
r
r
r
r
Bits
Fields
Descriptions
31:26
Reserved
Must be kept at reset value.
25:10
DATA[15:0]
Store DATA of option bytes block after system reset.
9:2
USER[7:0]
Store USER of option bytes block after system reset.
1
SPC
Option bytes security protection code
0: no protection
1: protection
0
OBERR
Option bytes read error bit.
This bit is set by hardware when the option bytes and its complement byte do not
match, then the option bytes is set to 0xFF.
2.4.8. Erase/Program Protection register (FMC_WP)
Address offset: 0x20
Reset value: 0xXXXX XXXX
This register has to be accessed by word (32-bit)