GigaDevice Semiconductor GD32VF103 - Receive Message FIFO0 Register (CAN_RFIFO0); Receive Message FIFO1 Register (CAN_RFIFO1)

GD32VF103 User Manual
447
0: Mailbox 0 transmit is progressing
1: Mailbox 0 transmit finished
20.4.4. Receive message FIFO0 register (CAN_RFIFO0)
Address offset: 0x0C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
RFD0
RFO0
RFF0
Reserved
RFL0[1:0]
rs
rc_w1
rc_w1
r
Bits
Fields
Descriptions
31:6
Reserved
Must be kept at reset value
5
RFD0
Receive FIFO0 dequeue
This bit is set by the software to start dequeuing a frame from receive FIFO0.
This bit is reset by the hardware while the dequeuing is done.
4
RFO0
Receive FIFO0 overfull
This bit is set by hardware when receive FIFO0 is overfull and reset by software
when write 1 to this bit.
0: The receive FIFO0 is not overfull
1: The receive FIFO0 is overfull
3
RFF0
Receive FIFO0 full
This bit is set by hardware when receive FIFO0 is full and reset by software when
write 1 to this bit.
0: The receive FIFO0 is not full
1: The receive FIFO0 is full
2
Reserved
Must be kept at reset value
1:0
RFL0[1:0]
Receive FIFO0 length
These bits are the length of the receive FIFO0.
20.4.5. Receive message FIFO1 register (CAN_RFIFO1)
Address offset: 0x10
Reset value: 0x0000 0000