GigaDevice Semiconductor GD32VF103 - Clock Configure Register (I2 C_CKCFG)

GD32VF103 User Manual
378
7
DUMODF
Dual Flag in slave mode indicating which address is matched in Dual-Address mode
This bit is cleared by hardware after a STOP or a START condition or I2CEN=0
0: SADDR0 address matches
1: SADDR1 address matches
6
HSTSMB
SMBus Host Header detected in slave mode
This bit is cleared by hardware after a STOP or a START condition or I2CEN=0
0: No SMBus Host Header detected
1: SMBus Host Header detected
5
DEFSMB
Default address of SMBus Device
This bit is cleared by hardware after a STOP or a START condition or I2CEN=0.
0: The default address has not been received
1: The default address has been received for SMBus Device
4
RXGC
General call address (00h) received.
This bit is cleared by hardware after a STOP or a START condition or I2CEN=0.
0: No general call address (00h) received
1: General call address (00h) received
3
Reserved
Must be kept the reset value.
2
TR
Whether the I2C is a transmitter or a receiver
This bit is cleared by hardware after a STOP or a START condition or I2CEN=0 or
LOSTARB=1.
0: Receiver
1: Transmitter
1
I2CBSY
Busy flag
This bit is cleared by hardware after a STOP condition
0: No I2C communication.
1: I2C communication active.
0
MASTER
A flag indicating whether I2C block is in master or slave mode.
This bit is set by hardware when a START condition generates.
This bit is cleared by hardware after a STOP or a START condition or I2CEN=0 or
LOSTARB=1.
0: Slave mode
1: Master mode
17.4.8. Clock configure register (I2C_CKCFG)
Address offset: 0x1C
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)