GigaDevice Semiconductor GD32VF103 - Channel X Peripheral Base Address Register (Dma_Chxpaddr); Channel X Memory Base Address Register (Dma_Chxmaddr)

GD32VF103 User Manual
146
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
CNT[15:0]
Transfer counter
These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’.
This register indicates how many transfers remain. Once the channel is enabled, it
is read-only, and decreases after each DMA transfer. If the register is zero, no
transaction can be issued whether the channel is enabled or not. Once the
transmission of the channel is complete, the register can be reloaded automatically
by the previously programmed value if the channel is configured in circular mode.
9.5.5. Channel x peripheral base address register (DMA_CHxPADDR)
x = 0...6, where x is a channel number
Address offset: 0x10 + 0x14 × x
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
Note: Do not configure this register when channel is enabled.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PADDR[31:16]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PADDR[15:0]
rw
Bits
Fields
Descriptions
31:0
PADDR[31:0]
Peripheral base address
These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’.
When PWIDTH is 01 (16-bit), the LSB of these bits is ignored. Access is
automatically aligned to a half word address.
When PWIDTH is 10 (32-bit), the two LSBs of these bits are ignored. Access is
automatically aligned to a word address.
9.5.6. Channel x memory base address register (DMA_CHxMADDR)
x = 0...6, where x is a channel number
Address offset: 0x14 + 0x14 × x
Reset value: 0x0000 0000