GigaDevice Semiconductor GD32VF103 - Page 147

GD32VF103 User Manual
147
This register has to be accessed by word (32-bit)
Note: Do not configure this register when channel is enabled.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MADDR[31:16]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MADDR[15:0]
rw
Bits
Fields
Descriptions
31:0
MADDR[31:0]
Memory base address
These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’.
When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is
ignored. Access is automatically aligned to a half word address.
When MWIDTH in the DMA_CHxCTL register is 10 (32-bit), the two LSBs of these
bits are ignored. Access is automatically aligned to a word address.