GigaDevice Semiconductor GD32VF103 - List of Figures

GD32VF103 User Manual
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List of Figures
Figure 1-1. GD32VF103 system architecture ............................................................................................... 24
Figure 2-1. Process of page erase operation .............................................................................................. 34
Figure 2-2. Process of mass erase operation ............................................................................................. 35
Figure 2-3. Process of word program operation ........................................................................................ 37
Figure 3-1. Power supply overview ............................................................................................................... 48
Figure 3-2. Waveform of the POR/PDR ......................................................................................................... 50
Figure 3-3. Waveform of the LVD threshold ................................................................................................ 50
Figure 5-1. The system reset circuit ............................................................................................................. 63
Figure 5-2. Clock tree ...................................................................................................................................... 64
Figure 5-3. HXTAL clock source .................................................................................................................... 65
Figure 6-1. Block diagram of EXTI ................................................................................................................ 97
Figure 7.1. Basic structure of a standard I/O port bit .............................................................................. 103
Figure 7.2. Input configuration .................................................................................................................... 104
Figure 7.3. Output configuration ................................................................................................................. 105
Figure 7.4. Analog configuration ................................................................................................................. 106
Figure 7.5. Alternate function configuration ............................................................................................. 106
Figure 8-1. Block diagram of CRC calculation unit .................................................................................. 129
Figure 9-1. Block diagram of DMA .............................................................................................................. 134
Figure 9-2. Handshake mechanism ............................................................................................................. 136
Figure 9-3. DMA interrupt logic .................................................................................................................... 138
Figure 9-4. DMA0 request mapping ............................................................................................................ 139
Figure 9-5. DMA1 request mapping ............................................................................................................ 140
Figure 11-1. ADC module block diagram ................................................................................................... 154
Figure 11-2. Single conversion mode ......................................................................................................... 156
Figure 11-3. Continuous conversion mode ............................................................................................... 157
Figure 11-4. Scan conversion mode, continuous disable ...................................................................... 158
Figure 11-5. Scan conversion mode, continuous enable ....................................................................... 159
Figure 11-6. Discontinuous conversion mode .......................................................................................... 160
Figure 11-7. Auto-insertion, CNT = 1 .......................................................................................................... 161
Figure 11-8. Triggered insertion .................................................................................................................. 161
Figure 11-9. 12-bit Data alignment .............................................................................................................. 162
Figure 11-10. 6-bit Data alignment .............................................................................................................. 162
Figure 11-11. 20-bit to 16-bit result truncation .......................................................................................... 165
Figure 11-12. Numerical example with 5-bits shift and rounding .......................................................... 166
Figure 11-13. ADC sync block diagram ...................................................................................................... 167
Figure 11-14. Regular parallel mode on 16 channels............................................................................... 168
Figure 11-15. Inserted parallel mode on 4 channels ................................................................................ 169
Figure 11-16. Follow-up fast mode on 1 channel in continuous conversion mode ........................... 169
Figure 11-17. Follow-up slow mode on 1 channel .................................................................................... 170
Figure 11-18. Trigger rotation: inserted channel group .......................................................................... 171