GigaDevice Semiconductor GD32VF103 - Register Definition; Interrupt Flag Register (DMA_INTF)

GD32VF103 User Manual
142
9.5. Register definition
DMA0 base address: 0x4002 0000
DMA1 base address: 0x4002 0400
Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the following
registers are not suitable for DMA1.
9.5.1. Interrupt flag register (DMA_INTF)
Address offset: 0x00
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
ERRIF6
HTFIF6
FTFIF6
GIF6
ERRIF5
HTFIF5
FTFIF5
GIF5
ERRIF4
HTFIF4
FTFIF4
GIF4
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERRIF3
HTFIF3
FTFIF3
GIF3
ERRIF2
HTFIF2
FTFIF2
GIF2
ERRIF1
HTFIF1
FTFIF1
GIF1
ERRIF0
HTFIF0
FTFIF0
GIF0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits
Fields
Descriptions
31:28
Reserved
Must be kept at reset value.
27/23/19/
15/11/7/3
ERRIFx
Error flag of channel x (x=0…6)
Hardware set and software cleared by configuring DMA_INTC register.
0: Transfer error has not occurred on channel x
1: Transfer error has occurred on channel x
26/22/18/
14/10/6/2
HTFIFx
Half transfer finish flag of channel x (x=0…6)
Hardware set and software cleared by configuring DMA_INTC register.
0: Half number of transfer has not finished on channel x
1: Half number of transfer has finished on channel x
25/21/17/
13/9/5/1
FTFIFx
Full Transfer finish flag of channel x (x=0…6)
Hardware set and software cleared by configuring DMA_INTC register.
0: Transfer has not finished on channel x
1: Transfer has finished on channel x
24/20/16/
12/8/4/0
GIFx
Global interrupt flag of channel x (x=0…6)
Hardware set and software cleared by configuring DMA_INTC register.
0: None of ERRIF, HTFIF or FTFIF occurs on channel x
1: At least one of ERRIF, HTFIF or FTFIF occurs on channel x