GigaDevice Semiconductor GD32VF103 - ADC Registers; Status Register (ADC_STAT)

GD32VF103 User Manual
174
11.8. ADC registers
ADC0 base address: 0x4001 2400
ADC1 base address: 0x4001 2800
11.8.1. Status register (ADC_STAT)
Address offset: 0x00
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
STRC
STIC
EOIC
EOC
WDE
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
Bits
Fields
Descriptions
31:5
Reserved
Must be kept at reset value
4
STRC
Start flag of regular channel group
0: No regular channel group started
1: Regular channel group started
Set by hardware when regular channel conversion starts.
Cleared by software writing 0 to it.
3
STIC
Start flag of inserted channel group
0: No inserted channel group started
1: Inserted channel group started
Set by hardware when inserted channel group conversion starts.
Cleared by software writing 0 to it.
2
EOIC
End of inserted group conversion flag
0: No end of inserted group conversion
1: End of inserted group conversion
Set by hardware at the end of all inserted group channel conversion.
Cleared by software writing 0 to it.
1
EOC
End of group conversion flag
0: No end of group conversion
1: End of group conversion
Set by hardware at the end of a regular or inserted group channel conversion.