GigaDevice Semiconductor GD32VF103 - DAC0 12-Bit Right-Aligned Data Holding Register (DAC0_R12 DH); DAC0 12-Bit Left-Aligned Data Holding Register (DAC0_L12 DH)

GD32VF103 User Manual
196
w
w
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value
1
SWTR1
DAC1 software trigger, cleared by hardware
0: Software trigger disabled
1: Software trigger enabled
0
SWTR0
DAC0 software trigger, cleared by hardware
0: Software trigger disabled
1: Software trigger enabled
12.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH)
Address offset: 0x08
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DAC0_DH[11:0]
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Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value
11:0
DAC0_DH[11:0]
DAC0 12-bit right-aligned data
These bits specify the data that is to be converted by DAC0.
12.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH)
Address offset: 0x0C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC0_DH[11:0]
Reserved
rw