GigaDevice Semiconductor GD32VF103 - Table 19-6. Multiplex Mode Related Registers Configuration

GD32VF103 User Manual
422
Table 19-6. Multiplex mode related registers configuration
EXMC_SNCTLx
Bit Position
Bit Name
Reference Setting Value
31-16
Reserved
0x0000
15
ASYNCWAIT
Depends on memory
14
Reserved
0x0
13
NRWTEN
0x0
12
WREN
Depends on memory
11:10
Reserved
0x0
9
NRWTPOL
Meaningful only when the bit 15 is set to 1
8-7
Reserved
0x1
6
NREN
0x1
5-4
NRW
Depends on memory
3-2
NRTP
0x2:NOR Flash
1
NRMUX
0x1
0
NRBKEN
0x1
EXMC_SNTCFGx
31-20
Reserved
0x0
19-16
BUSLAT
Minimum time between EXMC_NE[0] rising edge
to EXMC_NE[0] falling edge
15-8
DSET
Depends on memory and user
7-4
AHLD
Depends on memory and user
3-0
ASET
Depends on memory and user
Wait timing of asynchronous communication
Wait feature is controlled by the bit ASYNCWAIT in register EXMC_SNCTLx. During extern
memory access, data setup phase will be automatically extended by the active
EXMC_NWAIT signal if ASYNCWAIT bit is set. The extend time is calculated as follows:
If memory wait signal is aligned to EXMC_NOE/ EXMC_NWE:


 

 
If memory wait signal is aligned to EXMC_NE:
If 

   

 



 󰇛

 

 

󰇜  
Otherwise


  