GigaDevice Semiconductor GD32VF103 - Page Erase; Read Operations; Unlock the FMC_CTL Registers

GD32VF103 User Manual
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Note: The Information Block stores the boot loader. This block cannot be programmed or
erased by user.
2.3.2. Read operations
The flash can be addressed directly as a common memory space. Any instruction fetch and
the data access from the flash are through the IBUS or DBUS from the CPU.
2.3.3. Unlock the FMC_CTL registers
After reset, the FMC_CTL registers are not accessible in write mode, and the LK bit in
FMC_CTL register is 1. An unlocking sequence consists of two write operations to the
FMC_KEY register to open the access to the FMC_CTL register. The two write operations are
writing 0x45670123 and 0xCDEF89AB to the FMC_KEY register. After the two write
operations, the LK bit in FMC_CTL register is reset to 0 by hardware. The software can lock
the FMC_CTL again by setting the LK bit in FMC_CTL register to 1. Any wrong operations to
the FMC_KEY will set the LK bit to 1, and lock FMC_CTL register, and lead to a bus error.
The OBPG bit and OBER bit in FMC_CTL are still protected even the FMC_CTL is unlocked.
The unlocking sequence is two write operations, which are writing 0x45670123 and
0xCDEF89AB to FMC_OBKEY register. And then the hardware sets the OBWEN bit in
FMC_CTL register to 1. The software can reset OBWEN bit to 0 to protect the OBPG bit and
OBER bit in FMC_CTL register again.
2.3.4. Page erase
The FMC provides a page erase function which is used to initialize the contents of a main
flash memory page to a high state. Each page can be erased independently without affecting
the contents of other pages. The following steps show the access sequence of the registers
for a page erase operation.
 Unlock the FMC_CTL registers if necessary.
 Check the BUSY bit in FMC_STAT registers to confirm that no flash memory operation
is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished.
 Set the PER bit in FMC_CTL registers.
 Write the page absolute address (0x08XX XXXX) into the FMC_ADDR registers.
 Send the page erase command to the FMC by setting the START bit in FMC_CTL
registers.
 Wait until all the operations have finished by checking the value of the BUSY bit in
FMC_STAT registers.
 Read and verify the page if required using a DBUS access.
When the operation is executed successfully, the ENDF in FMC_STAT registers is set, and
an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL registers is set. Note
that a correct target page address must be confirmed. Or the software may run out of control