GigaDevice Semiconductor GD32VF103 - Oversample Control Register (ADC_OVSAMPCTL)

GD32VF103 User Manual
186
11.8.15. Oversample control register (ADC_OVSAMPCTL)
Address offset: 0x80
Reset value: 0x0000_0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DRES[1:0]
Reserved
TOVS
OVSS[3:0]
OVSR[2:0]
Reserved
OVSEN
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:14
Reserved
Must be kept at reset value.
13:12
DRES[1:0]
ADC resolution
00: 12bit;
01: 10bit;
10: 8bit;
11: 6bit
11:10
Reserved
Must be kept at reset value
9
TOVS
Triggered Oversampling
This bit is set and cleared by software.
0: All oversampled conversions for a channel are done consecutively after a trigger
1: Each conversion needs a trigger for a oversampled channel and the number of
triggers is determined by the oversampling ratio(OVSR[2:0]).
Note: Software is allowed to write this bit only when ADCON=0 (which ensures that
no conversion is ongoing).
8:5
OVSS[3:0]
Oversampling shift
This bit is set and cleared by software.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Other codes reserved
Note: Software is allowed to write this bit only when ADCON =0 (which ensures that