GigaDevice Semiconductor GD32VF103 - Reset Source;Clock Register (RCU_RSTSCK)

GD32VF103 User Manual
88
Bits
Fields
Descriptions
31:17
Reserved
Must be kept at reset value
16
BKPRST
Backup domain reset
This bit is set and reset by software.
0: No reset
1: Resets Backup domain
15
RTCEN
RTC clock enable
This bit is set and reset by software.
0: Disabled RTC clock
1: Enabled RTC clock
14:10
Reserved
Must be kept at reset value
9:8
RTCSRC[1:0]
RTC clock entry selection
Set and reset by software to control the RTC clock source. Once the RTC clock
source has been selected, it cannot be changed anymore unless the Backup
domain is reset.
00: No clock selected
01: CK_LXTAL selected as RTC source clock
10: CK_IRC40K selected as RTC source clock
11: (CK_HXTAL / 128) selected as RTC source clock
7:3
Reserved
Must be kept at reset value
2
LXTALBPS
LXTAL bypass mode enable
Set and reset by software.
0: Disable the LXTAL Bypass mode
1: Enable the LXTAL Bypass mode
1
LXTALSTB
Low speed crystal oscillator stabilization flag
Set by hardware to indicate if the LXTAL output clock is stable and ready for use.
0: LXTAL is not stable
1: LXTAL is stable
0
LXTALEN
LXTAL enable
Set and reset by software.
0: Disable LXTAL
1: Enable LXTAL
5.3.10. Reset source/clock register (RCU_RSTSCK)
Address offset: 0x24
Reset value: 0x0C00 0000, ALL reset flags reset by power Reset only, RSTFC/IRC40KEN
reset by system reset.