GigaDevice Semiconductor GD32VF103 - Guard Time and Prescaler Register (USART_GP)

GD32VF103 User Manual
352
0: Disable NACK transmission
1: Enable NACK transmission
This bit field cannot be written when the USART is enabled (UEN=1).
This bit is reserved for UART3/4.
3
HDEN
Half-duplex enable
This bit enables the half-duplex USART mode.
0: Half duplex mode is disabled
1: Half duplex mode is enabled
This bit field cannot be written when the USART is enabled (UEN=1).
2
IRLP
IrDA low-power
This bit selects low-power mode of IrDA mode.
0: Normal mode
1: Low-power mode
This bit field cannot be written when the USART is enabled (UEN=1).
1
IREN
IrDA mode enable
This bit enables the IrDA mode of USART.
0: IrDA disabled
1: IrDA enabled
This bit field cannot be written when the USART is enabled (UEN=1).
This bit is reserved in USART1.
0
ERRIE
Error interrupt enable
When DMA request for reception is enabled (DENR=1), if this bit is set, an interrupt
occurs when any one of the FERR, ORERR and NERR bits in USART_STAT is set.
0: Error interrupt disabled
1: Error interrupt enabled
16.4.7. Guard time and prescaler register (USART_GP)
Address offset: 0x18
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GUAT[7:0]
PSC[7:0]
rw
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept the reset value.