GigaDevice Semiconductor GD32VF103 - Figure 15-31. Pause TIMER0 with Enable Signal of TIMER2; Figure 15-32. Pause TIMER0 with O0 CPREF Signal of Timer2

GD32VF103 User Manual
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Figure 15-31. Pause TIMER0 with enable signal of TIMER2
TIMER_CK
TIMER2_CNT_REG
TIMER0_CNT_REG
TIMER2_CEN
61
62
63
11
12
13
TIMER0_TRGIF
In this example, we also can use O0CPRE as trigger source instead of enable signal output.
Do as follow:
1. Configure TIMER2 in master mode and output compare 0 prepare signal (O0CPRE) as
trigger output (MMS=3’b100 in the TIMER2_CTL1 register).
2. Configure the TIMER2 O0CPRE waveform (TIMER2_CHCTL0 register).
3. Configure TIMER0 to get the input trigger from TIMER2 (TRGS=3’b010 in the
TIMERx_SMCFG register).
4. Configure TIMER0 in pause mode (SMC=3’b101 in TIMER0_SMCFG register).
5. Enable TIMER0 by writing ‘1 in the CEN bit (TIMER0_CTL0 register).
6. Start TIMER2 by writing ‘1 in the CEN bit (TIMER2_CTL0 register).
Figure 15-32. Pause TIMER0 with O0CPREF signal of Timer2
TIMER_CK
TIMER2_CNT_REG
TIMER0_CNT_REG
TIMER2_CEN
61
62
63
11
12
13
TIMER0_TRGIF
 Using an external trigger to start 2 timers synchronously
We configure the start of TIMER0 triggered by the enable signal of TIMER2, and TIMER2 is
triggered by its CI0 input rises edge. To ensure 2 timers start synchronously, TIMER2 must
be configured in Master/Slave mode. Do as follow:
1. Configure TIMER2 in slave mode to get the input trigger from CI0 (TRGS=3’b100 in the
TIMER2_SMCFG register).
2. Configure TIMER2 in event mode (SMC=3’b110 in the TIMER2_SMCFG register).