GigaDevice Semiconductor GD32VF103 - AHB Reset Register (RCU_AHBRST)

GD32VF103 User Manual
90
1: External PIN reset generated
25
Reserved
Must be kept at reset value
24
RSTFC
Reset flag clear
This bit is set by software to clear all reset flags.
0: Not clear reset flags
1: Clear reset flags
23:2
Reserved
Must be kept at reset value
1
IRC40KSTB
IRC40K stabilization flag
Set by hardware to indicate if the IRC40K output clock is stable and ready for use.
0: IRC40K is not stable
1: IRC40K is stable
0
IRC40KEN
IRC40K enable
Set and reset by software.
0: Disable IRC40K
1: Enable IRC40K
5.3.11. AHB reset register (RCU_AHBRST)
Address offset: 0x28
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
USBFSR
ST
Reserved
rw
Bits
Fields
Descriptions
31:13
Reserved
Must be kept at reset value
12
USBFSRST
USBFS reset
This bit is set and reset by software.
0: No reset
1: Reset the USBFS
11:0
Reserved
Must be kept at reset value