GigaDevice Semiconductor GD32VF103 - I2 S Clock Prescaler Register (SPI_I2 SPSC)

GD32VF103 User Manual
414
This bit should be configured when I2S is disabled.
This bit is not used in SPI mode.
6
Reserved
Must be kept at reset value.
5:4
I2SSTD[1:0]
I2S standard selection
00: I2S Phillips standard
01: MSB justified standard
10: LSB justified standard
11: PCM standard
These bits should be configured when I2S is disabled.
These bits are not used in SPI mode.
3
CKPL
Idle state clock polarity
0: The idle state of I2S_CK is low level
1: The idle state of I2S_CK is high level
This bit should be configured when I2S is disabled.
This bit is not used in SPI mode.
2:1
DTLEN[1:0]
Data length
00: 16 bits
01: 24 bits
10: 32 bits
11: Reserved
These bits should be configured when I2S mode is disabled.
These bits are not used in SPI mode.
0
CHLEN
Channel length
0: 16 bits
1: 32 bits
The channel length must be equal to or greater than the data length.
This bit should be configured when I2S mode is disabled.
This bit is not used in SPI mode.
18.11.9. I2S clock prescaler register (SPI_I2SPSC)
Address offset: 0x20
Reset value: 0x0002
This register can be accessed by half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
MCKOEN
OF
DIV[7:0]
rw
rw
rw