GigaDevice Semiconductor GD32VF103 - Register Definition; Port Control Register 0 (Gpiox_Ctl0, X=A

GD32VF103 User Manual
113
7.5. Register definition
AFIO base address: 0x4001 0000
GPIOA base address: 0x4001 0800
GPIOB base address: 0x4001 0C00
GPIOC base address: 0x4001 1000
GPIOD base address: 0x4001 1400
GPIOE base address: 0x4001 1800
7.5.1. Port control register 0 (GPIOx_CTL0, x=A..E)
Address offset: 0x00
Reset value: 0x4444 4444
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CTL7[1:0]
MD7[1:0]
CTL6[1:0]
MD6[1:0]
CTL5[1:0]
MD5[1:0]
CTL4[1:0]
MD4[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CTL3[1:0]
MD3[1:0]
CTL2[1:0]
MD2[1:0]
CTL1[1:0]
MD1[1:0]
CTL0[1:0]
MD0[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:30
CTL7[1:0]
Port 7 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
29:28
MD7[1:0]
Port 7 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
27:26
CTL6[1:0]
Port 6 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
25:24
MD6[1:0]
Port 6 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
23:22
CTL5[1:0]
Port 5 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
21:20
MD5[1:0]
Port 5 mode bits
These bits are set and cleared by software