GigaDevice Semiconductor GD32VF103 - RTC Divider High Register (RTC_DIVH); RTC Divider Low Register (RTC_DIVL); RTC Prescaler Low Register (RTC_PSCL)

GD32VF103 User Manual
219
Bits
Fields
Descriptions
31:4
Reserved
Must be kept at reset value
3:0
PSC[19:16]
RTC prescaler value high
14.4.4. RTC prescaler low register (RTC_PSCL)
Address offset: 0x0C
Reset value: 0x8000
This register can be accessed by half-word (16-bit) or word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PSC[15:0]
w
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:0
PSC[15:0]
RTC prescaler value low
The frequency of SC_CLK is the RTCCLK frequency divided by (PSC[19:0]+1).
14.4.5. RTC divider high register (RTC_DIVH)
Address offset: 0x10
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DIV[19:16]
r
Bits
Fields
Descriptions
31:4
Reserved
Must be kept at reset value
3:0
DIV[19:16]
RTC divider value high
14.4.6. RTC divider low register (RTC_DIVL)
Address offset: 0x14
Reset value: 0x8000
This register can be accessed by half-word (16-bit) or word (32-bit)