GigaDevice Semiconductor GD32VF103 - RTC Prescaler High Register (RTC_PSCH)

GD32VF103 User Manual
218
Bits
Fields
Descriptions
31:6
Reserved
Must be kept at reset value
5
LWOFF
Last write operation finished flag
0: Last write operation on RTC registers did not finished.
1: Last write operation on RTC registers finished.
4
CMF
Configuration mode flag
0: Exit configuration mode.
1: Enter configuration mode.
3
RSYNF
Registers synchronized flag
0: Registers not yet synchronized with the APB1 clock.
1: Registers synchronized with the APB1 clock.
2
OVIF
Overflow interrupt flag
0: Overflow event not detected
1: Overflow event detected. An interrupt will occur if the OVIE bit is set in
RTC_INTEN.
1
ALRMIF
Alarm interrupt flag
0: Alarm event not detected
1: Alarm event detected. An interrupt named RTC global interrupt will occur if the
ALRMIE bit is set in RTC_INTEN. And another interrupt named the RTC Alarm
interrupt will occur if the EXTI 17 is enabled in interrupt mode.
0
SCIF
Second interrupt flag
0: Second event not detected.
1: Second event detected. An interrupt will occur if the SCIE bit is set in
RTC_INTEN.
Set by hardware when the divider reloads the value in RTC_PSCH/L, thus
incrementing the RTC counter.
14.4.3. RTC prescaler high register (RTC_PSCH)
Address offset: 0x08
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
PSC[19:16]
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