GD32VF103 User Manual
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2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1
(the output of CHx_ON is enabled),
If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level;
If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(high) level.
When CH0_O and CH0_ON are output at the same time, the specific outputs of CH0_O and
CH0_ON are related to the relevant bits (ROS, IOS, POE and DTCFG bits) in the
TIMERx_CCHP register. Please refer to Complementary outputs for more details.
In output compare mode, the TIMERx can generate timed pulses with programmable position,
polarity, duration and frequency. When the counter matches the value in the TIMERx_CHxCV
register of an output compare channel, the channel (n) output can be set, cleared, or toggled
based on CHxCOMCTL. When the counter reaches the value in the TIMERx_CHxCV register,
the CHxIF bit will be set and the channel (n) interrupt is generated if CHxIE = 1. And the DMA
request will be asserted, if CxCDE=1.
So the process can be divided into several steps as below:
Step1: Clock Configuration. Such as clock source, clock prescaler and so on.
Step2: Compare mode configuration.
Set the shadow enable mode by CHxCOMSEN
Set the output mode (set/clear/toggle) by CHxCOMCTL.
Select the active polarity by CHxP/CHxNP
Enable the output by CHxEN
Step3: Interrupt/DMA-request enable configuration by CHxIE/CHxDEN.
Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV
The TIMERx_CHxCV can be changed ongoing to meet the expected waveform.
Step5: Start the counter by configuring CEN to 1.
Figure 15-15. Output-compare in three modes show the three compare modes
toggle/set/clear. CAR=0x63, CHxVAL=0x3
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