GigaDevice Semiconductor GD32VF103 - Figure 11-11. 20-Bit to 16-Bit Result Truncation; Figure 11-12. Numerical Example with 5-Bits Shift and Rounding; On-Chip Hardware Oversampling

GD32VF103 User Manual
165
DRES[1:0]
bits
t
CONV
(ADC clock
cycles)
t
CONV
(ns) at
f
ADC
=14MHz
t
SMPL
(min)
(ADC clock
cycles)
t
ADC
(ADC clock
cycles)
t
ADC
(us) at
f
ADC
=14MHz
6
6.5
464 ns
1.5
8
571 ns
11.4.13. On-chip hardware oversampling
The on-chip hardware oversampling circuit performs data preprocessing to offload the CPU.
It can handle multiple conversions and average them into a single data with increased data
width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted,
and D
out
(n) is the n-th output digital signal of the ADC:
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





󰇛

󰇜


(11-1)
The on-chip hardware oversampling circuit performs the following functions: summing and bit
right shifting. The oversampling ratio N is defined by the OVSR[2:0] bits in the
ADC_OVSAMPCTL register. It can range from 2x to 256x. The division coefficient M means
bit right shifting up to 8-bit. It is configured through the OVSS[3:0] bits in the
ADC_OVSAMPCTL register.
The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right.
The upper bits of the result are then truncated, keeping only the 16 least significant bits
rounded to the nearest value using the least significant bits left apart by the shifting, before
being finally transferred into the data register.
Figure 11-11. 20-bit to 16-bit result truncation
Raw 20-bit data
19 15 11 7 3 0
15 11 7 3 0
Shifting
Truncation and
rounding
Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result
are simply truncated.
Figure 11-12. Numerical example with 5-bits shift and rounding shows a numerical