GigaDevice Semiconductor GD32VF103 - Deep-Sleep Mode Voltage Register (RCU_DSV)

GD32VF103 User Manual
93
0100: PREDV0 input source clock divided by 5
0101: PREDV0 input source clock divided by 6
0110: PREDV0 input source clock divided by 7
0111: PREDV0 input source clock divided by 8
1000: PREDV0 input source clock divided by 9
1001: PREDV0 input source clock divided by 10
1010: PREDV0 input source clock divided by 11
1011: PREDV0 input source clock divided by 12
1100: PREDV0 input source clock divided by 13
1101: PREDV0 input source clock divided by 14
1110: PREDV0 input source clock divided by 15
1111: PREDV0 input source clock divided by 16
5.3.13. Deep-sleep mode voltage register (RCU_DSV)
Address offset: 0x34
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DSLPVS[1:0]
rw
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value
1:0
DSLPVS[1:0]
Deep-sleep mode voltage select
These bits are set and reset by software
00 : The core voltage is 1.2V in Deep-sleep mode
01 : The core voltage is 1.1V in Deep-sleep mode
10 : The core voltage is 1.0V in Deep-sleep mode
11
: The core voltage is 0.9V in Deep-sleep mode