GigaDevice Semiconductor GD32VF103 - Tamper Pin Control Register (BKP_TPCTL); Tamper Control and Status Register (BKP_TPCS)

GD32VF103 User Manual
60
1: Enable RTC clock calibration output
When enable, the TAMPER pin will output a clock with the frequency f
RTCCLK
/64.
ASOEN has the priority over COEN. When ASOEN is set, the TAMPER pin will
output the RTC alarm or second signal whether COEN is set or not.
6:0
RCCV[6:0]
RTC clock calibration value
The value indicates how many clock pulses are ignored or added every 2^20 RTC
clock pulses.
4.4.3. Tamper pin control register (BKP_TPCTL)
Address offset: 0x30
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TPAL
TPEN
rw
rw
Bits
Fields
Descriptions
15:2
Reserved
Must be kept at reset value.
1
TPAL
TAMPER pin active level
0: The TAMPER pin is active high
1: The TAMPER pin is active low
0
TPEN
TAMPER detection enable
0: The TAMPER pin is free for GPIO functions
1: The TAMPER pin is dedicated for the Backup Reset function. The active level on
the TAMPER pin resets all data of the BKP_DATAx registers.
4.4.4. Tamper control and status register (BKP_TPCS)
Address offset: 0x34
Reset value: 0x0000(bit 2 reset by a system reset or the wake-up from Standby mode)
This register can be accessed by half-word (16-bit) or word (32-bit)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TIF
TEF
Reserved
TPIE
TIR
TER
r
r
rw
w
w
Bits
Fields
Descriptions
15:10
Reserved
Must be kept at reset value.