GigaDevice Semiconductor GD32VF103 - Page 61

GD32VF103 User Manual
61
9
TIF
Tamper interrupt flag
0: No tamper interrupt occurred
1: A tamper interrupt occurred
This bit is reset by writing 1 to the TIR bit or the TPIE bit being 0.
8
TEF
Tamper event flag
0: No tamper event occurred
1: A tamper event occurred
This bit is reset by writing 1 to the TER bit.
7:3
Reserved
Must be kept at reset value.
2
TPIE
Tamper interrupt enable
0: Disable the tamper interrupt
1: Enable the tamper interrupt
1
TIR
Tamper interrupt reset
0: No effect
1: Reset the TIF bit
This bit is always read as 0.
0
TER
Tamper event reset
0: No effect
1: Reset the TEF bit
This bit is always read as 0.