GigaDevice Semiconductor GD32VF103 - AHB Enable Register (RCU_AHBEN)

GD32VF103 User Manual
82
1: Reset the TIMER1
5.3.6. AHB enable register (RCU_AHBEN)
Address offset: 0x14
Reset value: 0x0000 0014
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
USBFSE
N
Reserved
EXMCEN
Reserved
CRCEN
Reserved
FMCSPE
N
Reserved
SRAMSP
EN
DMA1EN
DMA0EN
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:13
Reserved
Must be kept at reset value
12
USBFSEN
USBFS clock enable
This bit is set and reset by software.
0: Disabled USBFS clock
1: Enabled USBFS clock
11:9
Reserved
Must be kept at reset value
8
EXMCEN
EXMC clock enable
This bit is set and reset by software.
0: Disabled EXMC clock
1: Enabled EXMC clock
7
Reserved
Must be kept at reset value
6
CRCEN
CRC clock enable
This bit is set and reset by software.
0: Disabled CRC clock
1: Enabled CRC clock
5
Reserved
Must be kept at reset value
4
FMCSPEN
FMC clock enable when sleep mode
This bit is set and reset by software to enable/disable FMC clock during Sleep
mode.
0: Disabled FMC clock during Sleep mode
1: Enabled FMC clock during Sleep mode