GigaDevice Semiconductor GD32VF103 - Register Definition

GD32VF103 User Manual
211
13.2.4. Register definition
WWDGT base address: 0x4000 2C00
Control register (WWDGT_CTL)
Address offset: 0x00
Reset value: 0x0000 007F
This register can be accessed by half-word (16-bit) or word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
WDGTEN
CNT[6:0]
rs
rw
Bits
Fields
Descriptions
31:8
Reserved
Must be kept at reset value.
7
WDGTEN
Start the window watchdog timer. Only can cleared by a hardware reset. Writing 0
has no effect.
0: Window watchdog timer disabled
1: Window watchdog timer enabled
6:0
CNT[6:0]
The value of the watchdog timer counter. A reset occurs when the value of this
counter decreases from 0x40 to 0x3F. When the value of this counter is greater than
the window value, writing this counter also causes a reset.
Configuration register (WWDGT_CFG)
Address offset: 0x04
Reset value: 0x0000 007F
This register can be accessed by half-word (16-bit) or word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
EWIE
PSC[1:0]
WIN[6:0]
rs
rw
rw
Bits
Fields
Descriptions
31:10
Reserved
Must be kept at reset value.