GigaDevice Semiconductor GD32VF103 - Control and Status Register (PMU_CS)

GD32VF103 User Manual
55
2
WURST
Wakeup Flag Reset
0: No effect
1: Reset the wakeup flag
This bit is always read as 0.
1
STBMOD
Standby Mode
0: Enter the Deep-sleep mode when the RISC-V enters SLEEPDEEP mode
1: Enter the Standby mode when the RISC-V enters SLEEPDEEP mode
0
LDOLP
LDO Low Power Mode
0: The LDO operates normally during the Deep-sleep mode
1: The LDO is in low power mode during the Deep-sleep mode
3.4.2. Control and status register (PMU_CS)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
This register can be accessed by half-word(16-bit) or word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
WUPEN
Reserved
LVDF
STBF
WUF
rw
r
r
r
Bits
Fields
Descriptions
31:9
Reserved
Must be kept at reset value.
8
WUPEN
WKUP Pin Enable
0: Disable WKUP pin function
1: Enable WKUP pin function
If WUPEN is set before entering the power saving mode, a rising edge on the WKUP
pin wakes up the system from the power saving mode. As the WKUP pin is active
high, the WKUP pin is internally configured to input pull down mode. And set this bit
will trigger a wakup event when the input changes to high.
7:3
Reserved
Must be kept at reset value.
2
LVDF
Low Voltage Detector Status Flag
0: Low Voltage event has not occurred (V
DD
is higher than the specified LVD
threshold)
1: Low Voltage event occurred (V
DD
is equal to or lower than the specified LVD
threshold)
Note: The LVD function is stopped in Standby mode.