GigaDevice Semiconductor GD32VF103 - DAC Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8 DH); DAC0 Data Output Register (DAC0_DO)

GD32VF103 User Manual
200
19:16
Reserved
Must be kept at reset value
15:4
DAC0_DH[11:0]
DAC0 12-bit left-aligned data
These bits specify the data that is to be converted by DAC0.
3:0
Reserved
Must be kept at reset value
12.4.11. DAC concurrent mode 8-bit right-aligned data holding register
(DACC_R8DH)
Address offset: 0x28
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC1_DH [7:0]
DAC0_DH [7:0]
rw
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:8
DAC1_DH[7:0]
DAC1 8-bit right-aligned data
These bits specify the MSB 8-bit of the data that is to be converted by DAC1.
7:0
DAC0_DH[7:0]
DAC0 8-bit right-aligned data
These bits specify the MSB 8-bit of the data that is to be converted by DAC0.
12.4.12. DAC0 data output register (DAC0_DO)
Address offset: 0x2C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DAC0_DO [11:0]
r