GD32VF103 User Manual
280
Figure 15-34. General Level 0 timer block diagram
=1
0
0
0 0
Input Logic
Synchronizer&Filter
&Edge Detector
Edge selector Prescaler
Trigger processor
Trigger Selector&Counter
Quadrate Decoder
Slave mode processor
Counter
External Trigger
Input logic
Polarity selection
Edge detector
Prescaler
Filter
TIMERx_CHxCV
Register /Interrupt
Register set and update
Interrupt collector and
controller
APB BUS
CK_TIMER
CH0_IN
CH1_IN
CH2_IN
CH3_IN
CI0
ITI0
ITI1
ITI2
ITI3
ETI
CAR
Output Logic
generation of outputs signals in
compare, PWM,and mixed modes
according to initialization, software
output mask, and polarity control
CH0_O
DMA controller
TIMERx_TRGO
.
Interrupt
CH1_O
CH2_O
CH3_O
Update
Trigger
Cap/Com
DMA REQ/ACK
TIMERx_CH0
TIMERx_CH1
TIMERx_CH2
TIMERx_CH3
TIMERx_TG
TIMERx_UP
PSC
PSC_CLK
TIMER_CK
req en/direct req set
ETIFP
15.2.4. Function overview
Clock selection
The clock source of the general level0 TIMER can be either the CK_TIMER or an alternate
clock source controlled by SMC bits (TIMERx_SMCFG bit[2:0]).
SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU.
The default clock source is the CK_TIMER for driving the counter prescaler when the slave
mode is disabled (SMC [2:0] == 3’b000). When the CEN is set, the CK_TIMER will be divided
by PSC value to generate PSC_CLK.
In this mode, the TIMER_CK which drives counter’s prescaler to count is equal to CK_TIMER
which is from RCU module.
If the slave mode controller is enabled by setting SMC [2:0] in the TIMERx_SMCFG register
to an available value including 0x1, 0x2, 0x3 and 0x7, the prescaler is clocked by other clock
sources selected by the TRGS [2:0] in the TIMERx_SMCFG register, more details will be
introduced later. When the slave mode control bits SMC [2:0] are set to 0x4, 0x5 or 0x6, the
internal clock TIMER_CK is the counter prescaler driving clock source.
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