GigaDevice Semiconductor GD32VF103 - Figure 15-39. Timing Chart of down Counting Mode, PSC=0;1

GD32VF103 User Manual
285
Figure 15-39. Timing chart of down counting mode, PSC=0/1
CEN
CNT_CLK(PSC_CLK)
CNT_REG
05 04 03 02 01 00
63 62 61 60 5F
5E 5C 5B
Update event (UPE)
Update interrupt flag (UPIF)
CNT_REG
04 03
Update event (UPE)
Update interrupt flag (UPIF)
Hardware set
Software clear
Hardware set
TIMERx_PSC PSC == 0
TIMERx_PSC PSC == 1
TIMER_CK
5A
000102 63 62 61
CNT_CLK(PSC_CLK)