GigaDevice Semiconductor GD32VF103 - Filter Control Register (CAN_FCTL); Filter Mode Configuration Register (CAN_FMCFG)

GD32VF103 User Manual
457
20.4.17. Filter control register (CAN_FCTL)
Address offset: 0x200
Reset value: 0x2A1C 0E01
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
HBC1F[5:0]
Reserved
FLD
rw
rw
Bits
Fields
Descriptions
31:14
Reserved
Must be kept at reset value
13:8
HBC1F[5:0]
Header bank of CAN1 filter
These bits are set and cleared by software to define the first bank for CAN1 filter.
Bank0 ~ Bank HBC1F-1 used to CAN0. Bank HBC1F ~ Bank27 used to CAN1.
When set 0, not bank used to CAN0. When set 28, not bank used to CAN1.
7:1
Reserved
Must be kept at reset value
0
FLD
Filter lock disable
0: Filter lock enable
1: Filter lock disable
20.4.18. Filter mode configuration register (CAN_FMCFG)
Address offset: 0x204
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit). This register can be modified only when
FLD bit in CAN_FCTL register is set.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
FMOD27
FMOD26
FMOD25
FMOD24
FMOD23
FMOD22
FMOD21
FMOD20
FMOD19
FMOD18
FMOD17
FMOD16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FMOD15
FMOD14
FMOD13
FMOD12
FMOD11
FMOD10
FMOD9
FMOD8
FMOD7
FMOD6
FMOD5
FMOD4
FMOD3
FMOD2
FMOD1
FMOD0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw