GigaDevice Semiconductor GD32VF103 - Clock Control Unit (CCTL)

GD32VF103 User Manual
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source (external or internal reset).
Figure 5-1. The system reset circuit
Filter
WWDGT_RSTn
FWDGT_RSTn
SW_RSTn
OB_STDBY_RSTn
OB_DPSLP_RSTn
POWER_RSTn
NRST
System Reset
min 20 us
pulse
generator
Backup domain reset
A backup domain reset is generated by setting the BKPRST bit in the Backup domain control
register or Backup domain power on reset (V
DD
or V
BAT
power on, if both supplies have
previously been powered off).
5.2. Clock control unit (CCTL)
5.2.1. Overview
The Clock Control unit provides a range of frequencies and clock functions. These include an
Internal 8M RC oscillator (IRC8M), a High Speed crystal oscillator (HXTAL), a Low Speed
Internal 40K RC oscillator (IRC40K), a Low Speed crystal oscillator (LXTAL), three Phase
Lock Loop (PLL), a HXTAL clock monitor, clock prescalers, clock multiplexers and clock
gating circuitry.
The clocks of the AHB, APB and RISC-V are derived from the system clock (CK_SYS) which
can source from the IRC8M, HXTAL or PLL. The maximum operating frequency of the system
clock (CK_SYS) can be up to 108 MHz. The Free Watchdog Timer has independent clock
source (IRC40K), and Real Time Clock (RTC) uses the IRC40K, LXTAL or HXTAL/128 as its
clock source.