GigaDevice Semiconductor GD32VF103 - Inserted Data Register X (Adc_Idatax) (X= 0; Regular Data Register (ADC_RDATA)

GD32VF103 User Manual
185
0
ISQ3
11.8.13. Inserted data register x (ADC_IDATAx) (x= 0..3)
Address offset: 0x3C + 0x4*x,(x=0..3)
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IDATAn[15:0]
r
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:0
IDATAn[15:0]
Inserted number n conversion data
These bits contain the number n conversion result, which is read only.
11.8.14. Regular data register (ADC_RDATA)
Address offset: 0x4C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADC1RDTR[15:0]
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDATA[15:0]
r
Bits
Fields
Descriptions
31:16
ADC1RDTR[15:0]
ADC1 regular channel data
In ADC0: In sync mode, these bits contain the regular data of ADC1.
In ADC1: these bits are not used.
15:0
RDATA[15:0]
Regular channel data
These bits contain the conversion result from regular channel, which is read only.