GigaDevice Semiconductor GD32VF103 - Inserted Channel Data Offset Register X (Adc_Ioffx) (X=0; Watchdog High Threshold Register (ADC_WDHT)

GD32VF103 User Manual
181
011: 28.5 cycles
100: 41.5 cycles
101: 55.5 cycles
110: 71.5 cycles
111: 239.5 cycles
11.8.6. Inserted channel data offset register x (ADC_IOFFx) (x=0..3)
Address offset: 0x14-0x20
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
IOFF[11:0]
rw
Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value
11:0
IOFF[11:0]
Data offset for inserted channel x
These bits will be subtracted from the raw converted data when converting inserted
channels. The conversion result can be read from in the ADC_IDATAx registers.
11.8.7. Watchdog high threshold register (ADC_WDHT)
Address offset: 0x24
Reset value: 0x0000 0FFF
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
WDHT[11:0]
rw
Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value
11:0
WDHT[11:0]
Analog watchdog high threshold