GigaDevice Semiconductor GD32VF103 - Control Register 1 (SPI_CTL1)

GD32VF103 User Manual
408
1
CKPL
Clock polarity selection
0: CLK pin is pulled low when SPI is idle
1: CLK pin is pulled high when SPI is idle
0
CKPH
Clock phase selection
0: Capture the first data at the first clock transition
1: Capture the first data at the second clock transition
18.11.2. Control register 1 (SPI_CTL1)
Address offset: 0x04
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TBEIE
RBNEIE
ERRIE
TMOD
NSSP
NSSDRV
DMATEN
DMAREN
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:8
Reserved
Must be kept at reset value.
7
TBEIE
Transmit buffer empty interrupt enable
0: TBE interrupt is disabled.
1: TBE interrupt is enabled. An interrupt is generated when the TBE bit is set.
6
RBNEIE
Receive buffer not empty interrupt enable
0: RBNE interrupt is disabled.
1: RBNE interrupt is enabled. An interrupt is generated when the RBNE bit is set.
5
ERRIE
Errors interrupt enable
0: Error interrupt is disabled.
1: Error interrupt is enabled. An interrupt is generated when the CRCERR bit, the
CONFERR bit, the RXORERR bit or the TXURERR bit is set.
4
TMOD
SPI TI mode enable
0: SPI TI mode disabled.
1: SPI TI mode enabled.
3
NSSP
SPI NSS pulse mode enable
0: SPI NSS pulse mode disabled.
1: SPI NSS pulse mode enabled.
2
NSSDRV
Drive NSS output
0: NSS output is disabled.