GigaDevice Semiconductor GD32VF103 - Page 407

GD32VF103 User Manual
407
SPI_DATA register. In receive-only mode, set this bit after the second last data is
received.
11
FF16
Data frame format
0: 8-bit data frame format
1: 16-bit data frame format
10
RO
Receive only mode
When BDEN is cleared, this bit determines the direction of transfer.
0: Full-duplex mode
1: Receive-only mode
9
SWNSSEN
NSS software mode enable
0: NSS hardware mode. The NSS level depends on NSS pin.
1: NSS software mode. The NSS level depends on SWNSS bit.
This bit has no meaning in SPI TI mode.
8
SWNSS
NSS pin selection in NSS software mode
0: NSS pin is pulled low
1: NSS pin is pulled high
This bit effects only when the SWNSSEN bit is set.
This bit has no meaning in SPI TI mode.
7
LF
LSB first mode
0: Transmit MSB first
1: Transmit LSB first
This bit has no meaning in SPI TI mode.
6
SPIEN
SPI enable
0: SPI peripheral is disabled
1: SPI peripheral is enabled
5:3
PSC[2:0]
Master clock prescaler selection
000: PCLK/2
001: PCLK/4
010: PCLK/8
011: PCLK/16
100: PCLK/32
101: PCLK/64
110: PCLK/128
111: PCLK/256
PCLK means PCLK2 when using SPI0 or PCLK1 when using SPI1 and SPI2.
2
MSTMOD
Master mode enable
0: Slave mode
1: Master mode