GigaDevice Semiconductor GD32VF103 - Register Definition; Control Register (CAN_CTL)

GD32VF103 User Manual
441
20.4. Register definition
CAN0 base address: 0x4000 6400
CAN1 base address: 0x4000 6800
20.4.1. Control register (CAN_CTL)
Address offset: 0x00
Reset value: 0x0001 0002
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DFZ
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SWRST
Reserved
TTC
ABOR
AWU
ARD
RFOD
TFO
SLPWMO
D
IWMOD
rs
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:17
Reserved
Must be kept at reset value
16
DFZ
Debug freeze
If the CANx_HOLD in DBG_CTL register is set, this bit define the CAN stop for
debug or work normal. If the CANx_HOLD in DBG_CTL register is clear, this bit take
not effect.
0: CAN reception and transmission working normal even during debug
1: CAN reception and transmission stop working during debug
15
SWRST
Software reset
0: No effect
1: Reset CAN with working mode of sleep. This bit is automatically reset to 0
14:8
Reserved
Must be kept at reset value
7
TTC
Time-triggered communication
0: Disable time-triggered communication
1: Enable time-triggered communication
6
ABOR
Automatic bus-off recovery
0: The bus-off state is left manually by software
1: The bus-off state is left automatically by hardware
5
AWU
Automatic wakeup
If this bit is set, the sleep mode left when CAN bus activity detected, and