GigaDevice Semiconductor GD32VF103 - Power and Clock Control Register (USBFS_PWRCLKCTL)

GD32VF103 User Manual
534
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:0
IEPTFS[15:0]
IN endpoint’s Tx FIFO space remaining
I
N endpoint’s Tx FIFO space remaining in 32-bit words:
0: FIFO is full
1: 1 word available
…
n: n words available
21.7.4. Power and clock control register (USBFS_PWRCLKCTL)
Address offset: 0x0E00
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SHCLK
SUCLK
rw
rw
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value
1
SHCLK
Stop HCLK
Stop the HCLK to save power.
0:HCLK is not stopped
1:HCLK is stopped
0
SUCLK
Stop the USB clock
Stop the USB clock to save power.
0:USB clock is not stopped
1:USB clock is stopped