GigaDevice Semiconductor GD32VF103 - Interrupt Enable Register (CAN_INTEN)

GD32VF103 User Manual
448
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
RFD1
RFO1
RFF1
Reserved
RFL1[1:0]
rs
rc_w1
rc_w1
r
Bits
Fields
Descriptions
31:6
Reserved
Must be kept at reset value
5
RFD1
Receive FIFO1 dequeue
This bit is set by the software to start dequeuing a frame from receive FIFO1.
This bit is reset by the hardware while the dequeuing is done.
4
RFO1
Receive FIFO1 overfull
This bit is set by hardware when receive FIFO1 is overfull and reset by software
when write 1 to this bit.
0: The receive FIFO1 is not overfull
1: The receive FIFO1 is overfull
3
RFF1
Receive FIFO1 full
This bit is set by hardware when receive FIFO1 is full and reset by software when
write 1 to this bit.
0: The receive FIFO1 is not full
1: The receive FIFO1 is full
2
Reserved
Must be kept at reset value
1:0
RFL1[1:0]
Receive FIFO1 length
These bits are the length of the receive FIFO1.
20.4.6. Interrupt enable register (CAN_INTEN)
Address offset: 0x14
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
SLPWIE
WIE
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERRIE
Reserved
ERRNIE
BOIE
PERRIE
WERRIE
Reserved
RFOIE1
RFFIE1
RFNEIE1
RFOIE0
RFFIE0
RFNEIE0
TMEIE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw