GigaDevice Semiconductor GD32VF103 - List of Tables

GD32VF103 User Manual
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List of Tables
Table 1-1. The interconnection relationship of the AHB interconnect matrix ....................................... 23
Table 1-2. Memory map of GD32VF103 devices ......................................................................................... 25
Table 1-3. Boot modes .................................................................................................................................... 29
Table 2-1. Base address and size for flash memory .................................................................................. 32
Table 2-2. Option byte ...................................................................................................................................... 38
Table 3-1. Power saving mode summary ..................................................................................................... 52
Table 5-1. Clock output 0 source select ....................................................................................................... 68
Table 5-2. 1.2V domain voltage selected in deep-sleep mode ................................................................. 68
Table 6-1. Interrupt vector table .................................................................................................................... 95
Table 6-2. EXTI source .................................................................................................................................... 98
Table 7.1. GPIO configuration table ............................................................................................................ 102
Table 7.2. Debug interface signals .............................................................................................................. 108
Table 7.3. Debug port mapping.................................................................................................................... 108
Table 7.4. TIMER0 alternate function remapping ...................................................................................... 109
Table 7.5. TIMER1 alternate function remapping ...................................................................................... 109
Table 7.6. TIMER2 alternate function remapping ...................................................................................... 109
Table 7.7. TIMER3 alternate function remapping ...................................................................................... 109
Table 7.8. TIMER4 alternate function remapping ...................................................................................... 110
Table 7.9. USART0 alternate function remapping ..................................................................................... 110
Table 7.10. USART1 alternate function remapping ................................................................................... 110
Table 7.11. USART2 alternate function remapping ................................................................................... 110
Table 7.12. I2C0 alternate function remapping .......................................................................................... 110
Table 7.13. SPI0 alternate function remapping .......................................................................................... 111
Table 7.14. SPI2/I2S2 alternate function remapping ................................................................................. 111
Table 7.15. CAN0 alternate function remapping ....................................................................................... 111
Table 7.16. CAN1 alternate function remapping ....................................................................................... 111
Table 7.17. OSC32 pins configuration......................................................................................................... 112
Table 7.18. OSC pins configuration ............................................................................................................. 112
Table 9-1. DMA transfer operation .............................................................................................................. 135
Table 9-2. Interrupt events ............................................................................................................................ 138
Table 9-3. DMA0 requests for each channel .............................................................................................. 140
Table 9-4. DMA1 requests for each channel .............................................................................................. 141
Table 11-1. ADC internal signals ................................................................................................................. 154
Table 11-2. ADC pins definition ................................................................................................................... 154
Table 11-3. External trigger for regular channels for ADC0 and ADC1 ................................................. 163
Table 11-4. External trigger for inserted channels for ADC0 and ADC1 ............................................... 163
Table 11-5. t
CONV
timings depending on resolution .................................................................................. 164
Table 11-6. Maximum output results vs N and M (Grayed values indicates truncation) ................... 166
Table 12-1. DAC pins ..................................................................................................................................... 189
Table 12-2. External triggers of DAC........................................................................................................... 190